The present invention relates to switch circuits comprising a plurality of scaled current steering switches which are selectively operable from one state to another in response to switching signals, and in particular, the invention relates to such a switch circuit in which time-skew resulting from failure of selected ones of the current steering switches to simultaneously switch from one state to the other in response to simultaneously applied switching signals is minimised. In particular, the invention relates to a compensating circuit for use with such a switch circuit for minimising time-skew. The invention also relates to a current steering digital to analogue converter (DAC) incorporating the compensating circuit. The invention also relates to a method for minimising time-skew in the selective switching of a plurality of scaled current steering switches from one state to another in response to respective simultaneously applied switching signals.
In current steering DACs digital data is converted into an equivalent analogue output current which corresponds to the digital word being converted. The analogue current is derived from the sum of the currents from a plurality of binarily weighted current sources, which are weighted to correspond to the bits of the digital word from the least significant bit (LSB), to the most significant bit (MSB). In the conversion process the currents from the current sources corresponding to the bits of the digital word are steered into summing nodes, one node representing true data bits, and one node representing false data bits. The summing nodes are terminated with respective terminating resistors, and the summed currents are converted into output voltages developed across the respective terminating resistors.
It is important that non-linearities between the digital data inputted to such a DAC, and the analogue output be kept to a minimum. Such non-linearities originate from errors in the weighting ratios of the analogue currents, and from dynamic errors arising from the steering of the currents into the respective nodes in response to the digital data. In practical implementations of current steering DACs the currents from the current sources are switched to the summing nodes through current steering analogue switches, which in an integrated circuit are typically MOS transistor switches. The switches, in general, are provided as dual switch pairs, one dual switch pair being provided for each current source. The switches are scaled in size in proportion to the current to be switched from the corresponding current sources. The dual switch pairs are responsive to switching signals which are in turn responsive to the corresponding individual digital data bits. One of the switches of each dual switch pair is responsive to a true signal, and the other is responsive to a false signal. It is important that the xe2x80x9conxe2x80x9d voltage across the switches for steering the currents from the current sources which is given by the following equation should be constant:
VSW=I0.2i.Roni=constant
where I0 represents the current of the current source corresponding to the LSB,
i represents the bit, from bit i=0 (LSB) to bit i=nxe2x88x921 (MSB), and
Roni represents the on resistance of the switch corresponding to bit i.
In MOS transistor switches the on resistance (Ron) is inversely proportional to the geometric size of the switch, and thus from the above equation for the switch voltage VSW the MOS transistor switch for switching the current sources corresponding to the respective bit i must be of size 2i times the size of the MOS transistor switch for switching the LSB. Thus, in an n bit DAC each MOS switch of the dual switch pair for switching the current of the current source corresponding to the MSB must be of size 2nxe2x88x921 times the size of one of the MOS switches of the dual switch pair for switching the current source corresponding to the LSB, and so on for the switches of the dual switch pairs corresponding to the bits 2nxe2x88x922, 2nxe2x88x923, and so on.
The size of a MOS transistor switch is determined by the area of the switch, which in turn is determined by the length and width of the switch. The length is determined by the distance between the source and the drain of the switch, and the width is determined by the width of the source and drain, this will be well known to those skilled in the art.
The MOS current steering switches are switched in response to the respective corresponding bits of the digital data word. Respective driver circuits corresponding to the dual switch pairs output appropriate true and false switching signals in response to the digital data word for selectively switching the switches of the dual switch pairs. The switching signals are applied to the gates of the corresponding MOS switches of the dual switch pairs, for appropriately switching the switches. The switching load presented by a MOS switch to a corresponding driver circuit is a capacitive load, and is proportional to the switch size, and thus, the switching load presented to the driver circuits by the respective MOS switches are scaled in proportion to the scaling of the MOS switches. The capacitive switching load results from parasitic capacitance between the gate and the source and the gate and the drain, respectively, of the MOS switch, and also between the gate and the silicon of the MOS switch which is referred to as bulk capacitance.
Digital data samples are received by a DAC from a data register which is clocked at a constant rate, and thus, each digital data word is provided to the driver circuits simultaneously, and the switching signals, which are derived from the digital data word by the driver circuits are similarly provided by the driver circuits to the switches simultaneously. However, due to the fact that the switching loads presented to the respective driver circuits by their corresponding MOS switches differ due to the scaling of the switches, the switches are not simultaneously switched. This leads to time-skewing during switching of the MOS switches, which in turn leads to inter-symbol-interference and harmonic distortion. This type of distortion can become dominant for high data sampling rates which are common in DACs, and also in direct digital synthesisers.
Time-skew of the analogue output signal can be readily understood with reference to FIG. 1 which illustrates the timing performance of a typical prior art n bit DAC. Waveform (ALSB) represents the output from the LSB register in response to a data word, and waveform (AMSB) represents the output of the MSB register in response to the data word. At time t0 both ALSB and AMSB go high. Waveform BLSB represents the output voltage of the switching signal of the driver circuit of the MOS switch corresponding to the LSB, while waveform BMSB represents the output voltage of the switching signal of the driver circuit of the MOS switch corresponding to the MSB. Waveform CLSB represents the state of the MOS switch corresponding to the LSB, while waveform CMSB represents the state of the MOS switch corresponding to the MSB. Waveform DLSB represents the current I0 flowing through the MOS switch corresponding to the LSB, while waveform DMSB represents the current flowing through the MOS switch corresponding to the MSB. The current waveform DMSB corresponding to the MSB which is I0.2(nxe2x88x921) is not to scale.
At time t0 the output from the LSB register and from the MSB register both go high simultaneously. Due to the capacitive switching load presented by the respective MOS switches corresponding to the LSB and the MSB to their corresponding driver circuits there is a time delay before the voltages of the switching signals from the driver circuits reach a level sufficient for switching the corresponding MOS switches. Due to the higher capacitive load presented by the MOS switch corresponding to the MSB than that presented by the MOS switch corresponding to the LSB, the time delay in switching the MOS switch corresponding to the MSB is greater than that for switching the MOS switch corresponding to the LSB. The MOS switch corresponding to the LSB switches from one state to the other at time tDLSB, while the MOS switch corresponding to the MSB switches from one state to the other at time tDMSB. Thus, the difference in the two time delays is xcex94t which is equal to tDMSBxe2x88x92tDLSB. Waveform E represents a summation (not to scale) of the currents through the MOS switches corresponding to the MSB and the LSB. The distortion due to the time delay xcex94t in switching is illustrated by the portion of the waveform between the points X and Y of waveform E during the switching time delay xcex94t. Similar time-skewing occurs when the respective LSB and MSB outputs from the register go low. Although the currents for the bits 1 to nxe2x88x922 have not been illustrated, similar time-skewing as a result of non-simultaneous switching of the corresponding MOS switches occurs in the analogue currents corresponding to all the bits.
In order to minimise dynamic errors due to time-skewing, driver circuits for switching the MOS switches in response to the digital data bits are commonly scaled to take account of the variation of the switching load presented by the respective MOS switches. However, the scaling range that can be implemented in driver circuits due to the general combined requirement to minimise time-skew and to achieve suitable fast switch control signal transitions is significantly limited. A further constraint arises due to the fact that the level of the switching signals must be adjusted to optimise the switching operation between switches responding to true and false data bits. Such optimisation may be contrary to the optimum driver scaling for some bits. In practice, known prior art methods for reducing time-skew fail to eliminate timing errors between switches responding to higher order data bits, namely, those in the MSBs range, and those responding to lower order bits, namely, those in the LSBs range.
Similar problems arise in other circuits where scaled analogue switches are provided for switching currents from scaled current sources.
Accordingly, there is therefore a need for a circuit which overcomes these problems. There is also a need for a DAC in which errors resulting from time-skewing are minimised, and there is a need for a method for minimising time-skewing in the selective switching of a plurality of scaled analogue switches from one state to another.
The present invention is directed towards providing such a circuit, a DAC and a method.
According to the invention there is provided a compensating circuit for providing switching load compensation for a plurality of scaled current steering switches selectively operable from one state to another state in response to respective switching signals, the compensating circuit comprising a scaled load compensating circuit for providing scaled switching load compensation for at least some of the current steering switches so that the switching loads presented to driver circuits of the respective current steering switches for switching thereof are substantially similar, thereby facilitating substantially simultaneous switching of selected ones of the switches from one of the states to the other state in response to simultaneously applied switching signals.
In one embodiment of the invention the compensating circuit comprises the driver circuits, and the driver circuits are substantially similar to each other.
In another embodiment of the invention the scaled load compensating circuit comprises a plurality of load compensating elements, one load compensating element being provided corresponding to each current steering switch for which switching load compensation is to be provided, the values of the switching load compensation provided by the respective load compensating elements being such that when combined with the switching load of the corresponding current steering switch, the combined switching load presented to the corresponding driver circuit is substantially similar for each current steering switch and its corresponding load compensating element.
In a further embodiment of the invention each load compensating element comprises a load compensating switch, the switching load compensation being derived from the switching load of the load compensating switch.
Preferably, each load compensating switch is of similar type to that of the corresponding current steering switch.
Advantageously, the load compensating switches are scaled so that the switching load compensation provided by the respective load compensating switches is complementary to the switching loads of the current steering switches.
In one embodiment of the invention the load compensating switch presenting the largest switching load compensation corresponds to the current steering switch presenting the smallest switching load for which switching load compensation is to be provided, and the load compensating switch presenting the smallest switching load compensation corresponds to the current steering switch presenting the largest switching load for which switching load compensation is to be provided.
Advantageously, the load compensating switches are binarily scaled in descending order for compensating for current steering switches which are binarily scaled in ascending order.
In one embodiment of the invention each load compensating switch is a non-load switching switch.
In another embodiment of the invention a load correcting element associated with each load compensating switch is provided for correcting for the difference between an ideal switching load of the corresponding load compensating switch if the load compensating switch were switching a load, and the actual switching load compensation provided by the load compensating switch. Preferably, each load compensating element provides capacitive switching load compensation.
In another embodiment of the invention a coupling compensating element is provided for at least some of the current steering switches for compensating for distortion resulting from switching signal coupling effects. Preferably, each coupling compensating element comprises a coupling compensating switch, and the coupling compensation is derived from the parasitic capacitance of the coupling compensating switch between the gate of the switch and the source and drain thereof. Advantageously, the source and drain of each coupling compensating switch are electrically connected together.
Additionally the invention provides a switch circuit comprising:
a plurality of scaled current steering switches selectively operable from one state to another state in response to respective switching signals, and
a scaled load compensating circuit for providing scaled switching load compensation for at least some of the current steering switches so that the switching loads presented to driver circuits of the respective current steering switches for switching thereof are substantially similar, thereby facilitating substantially simultaneous switching of selected ones of the switches from one of the states to the other state in response to simultaneously applied switching signals.
In one embodiment of the invention the switching circuit comprises the driver circuits, and the driver circuits are substantially similar to each other.
In another embodiment of the invention one load compensating element is provided for each current steering switch.
In another embodiment of the invention the switching circuit is implemented in an integrated circuit, and each current steering switch is a MOS switch, having a capacitive switching load, and each load compensating element providing a capacitive switching load compensation.
In another embodiment of the invention the current steering switches are provided in switch pairs, and the load compensating elements are provided in corresponding pairs.
Further the invention provides a current steering digital to analogue converter comprising:
a plurality of binarily scaled current steering switches operable from one state to another state in response to switching signals for selectively switching currents through selected ones of the current steering switches to a common node, and
a scaled load compensating circuit for providing scaled switching load compensation for at least some of the current steering switches so that the switching loads presented to driver circuits of the respective current steering switches for switching thereof are substantially similar, thereby facilitating substantially simultaneous switching of selected ones of the current steering switches from one of the states to the other state in response to the simultaneously applied switching signals.
In one embodiment of the invention the digital to analogue converter comprises the driver circuits, and the driver circuits are substantially similar to each other.
The invention also provides a method for minimising time-skew in the selective switching of a plurality of current steering switches from one state to another state in response to respective simultaneously applied switching signals, the method comprising the step of providing scaled load compensation for at least some of the current steering switches so that the switching loads presented to driver circuits of the respective current steering switches are substantially similar, thereby facilitating substantially simultaneous switching of selected ones of the current steering switches from one of the states to the other state in response to the simultaneously applied switching signals.
In one embodiment of the invention the driver circuits are provided to be substantially similar to each other.
In another embodiment of the invention one load compensating element is provided for each current steering switch. Preferably, each load compensating element is provided by a load compensating switch, the switching load compensation being derived from the switching load of the load compensating switch.
The advantages of the invention are many. By virtue of the fact that the switching loads presented to the driver circuits of the current steering switches are substantially similar, the selected ones of the current steering switches are simultaneously switched in response to the switching signals. Thus, time-skew in the analogue current output of the switching circuit is avoided. This is a particularly important advantage in current steering DACs, and in particular, in high speed current steering DACs, although, needless to say, the advantages of the invention may be achieved in any circuit which comprises scaled current steering switches. These advantages are achieved by virtue of the fact that the provision of the load compensating circuit ensures that the switching loads presented to the driver circuits of the respective current steering switches are substantially similar, and therefore, the driver circuits themselves can also be substantially similar to each other. This ensures that the selected ones of the current steering switches are simultaneously switched in response to the switching signals.
Additionally, by virtue of the fact that the switching loads of the current steering switches are compensated for such that the switching load presented to the respective driver circuits are similar, distortion in the analogue output resulting from coupling errors can more easily be corrected.
These and other advantages of the invention will be readily apparent to those skilled in the art from the following description of some preferred embodiments thereof, which are given by way of example only, with reference to the accompanying drawings.